Communication systems often transmit data with a clock embedded in a data stream, rather than being sent as a separate signal. When the data stream is received, a clock and data recovery circuit (CDR) recovers the embedded clock and retimes the received data to the recovered clock. Typically, a phase-locked loop (PLL) is used to perform the clock recovery operation. Such a PLL typically includes a phase detector, which receives the input data signal and a clock signal from a voltage-controlled oscillator (VCO). The phase detector generates an error signal, which is a function of the phase difference between the input data signal and the VCO clock signal. The phase detector may also include additional circuitry to generate the reconstructed data.
The data stream is used to transmit digital information at high data rates. For data to be reliably transmitted and received, a system typically has a low bit error rate (BER). Typically, the BER is determined by counting the number of data transitions occurring within a certain time frame of a data eye.
Oftentimes, a CDR is implemented in an integrated circuit along with additional components, such as a limit amplifier (LA) and other such components. The LA may receive a voltage signal from a transimpedance amplifier (TIA) or other amplifier, which amplifies an incoming converted optical signal. Instead of a LA, an automatic gain control (AGC) amplifier may be used.
The function of the limit amplifier is to produce a consistent waveform from a TIA output which can be used by the CDR, regardless of incoming optical energy. In addition to amplifying the input signal, the LA may provide an adjustable slicing level to compensate for an asymmetric noise characteristic present in the incoming data. A slicing level is the threshold voltage at which an incoming signal is determined to be either a “1” bit or a “0” bit. At low levels of optical energy (corresponding to a zero bit level for example), the noise current is low. At higher levels of optical energy (corresponding to a one bit), the noise current may be higher.
Further, asymmetry in voltage levels corresponding to “1” and “0” level bits may exist, as shown in FIG. 1, which is a timing diagram of a typical data eye of incoming data. As shown in FIG. 1, at a slicing level of 0 mV, the horizontal opening of the data eye 5 is smaller than the horizontal opening at a slicing level of −0.2 mV. Thus, a slicing level of zero may give a smaller amount of margin for the positive swing compared to the negative swing. In FIG. 1, the data eye 5 is shown to have its widest opening at a slicing level of −0.2 mV. If the slicing level is set to roughly −2 mV in the case shown, the margin is more symmetric and better results are possible. This asymmetry may require an introduction of an intentional offset to create the most reliable output. Thus, introducing a small offset serves to optimize noise margin and signal strength. Current approaches for determining a slice offset typically require additional circuitry, consuming semiconductor real estate and power.
Accordingly, a need exists for improved analysis of signal quality and an improved manner of determining a slice level offset for an amplifier in a signal path.